1. Field of the Invention
The invention relates to a frequency synthesizer, and more particularly to a low noise charge pump for use in a PLL (Phase-Locked Loop) based frequency synthesizer.
2. Description of the Related Art
In recent years, the rapid growth of cellular communications systems has motivated an increasing demand for high performance integrated radio frequency (RF) components. One of the most important building blocks of these systems is the local oscillator (LO). In modern RF transceivers, the oscillators are usually embedded in a synthesizer environment so as to achieve a precise definition of the output frequency. Phase-locked loop (PLL) techniques have been widely used in frequency synthesis to meet the stringent requirements of wireless standards, because under locked condition the output frequency of a PLL bears an exact relationship with the input frequency.
A PLL-based synthesis technique offers high integration level, low power dissipation, small chip area, high reliability, and predictable performance. The comparison frequency (i.e., the reference frequency at the phase detector) in an integer-N frequency synthesizer is equal to the channel spacing, or step size. Thus, the integer-N frequency synthesizer with small channel spacing is not suitable for a system requiring rapid frequency acquisition as the loop bandwidth must be narrow enough to maintain the system stability. Another drawback results from the inverse relationship between the channel spacing and in-band phase noise. As the channel spacing decreases, the divide ratio of the frequency divider for a given local oscillator frequency range must increase. The higher the divide ratio, the worse the phase noise inside the loop bandwidth close to carrier frequency. It is known that the in-band phase noise is higher than the system noise floor by approximately an amount of 20 log N dB, where N is the total divide ratio. The output spurs are also related to the loop bandwidth. Therefore, trade-offs are necessary in determining the loop bandwidth and loop performance.
A fractional-N frequency synthesis technique enables the use of comparison frequencies larger than the channel spacing. This technique is able to considerably reduce the divide ratio N in the loop for the same channel spacing as that in an integer-N synthesizer, while using the highest possible comparison frequency. The fractional-N synthesis has a significant beneficial effect on the in-band phase noise performance. The possibility of using a higher comparison frequency also opens up the way to a wider loop bandwidth, hence a faster lock transient. Using a comparison frequency higher than the channel spacing can reduce the reference spurs at the output. Nevertheless, the use of the fractional-N technique introduces periodic disturbances in the loop, resulting in large fractional spurs.
A fundamental element of the PLL is a charge-pump circuit, because this circuit dominates the output frequency of a voltage-controlled oscillator (VCO). To meet the high switching speed requirement of RF transceivers, a high-speed charge pump must be employed in the integrated circuit implementation. During the charge pump switching time, switching noise may introduce spikes onto the output. This is detrimental to the performance of the PLL or frequency synthesizer and, when implemented in an RF transceiver, ultimately degrades the signal quality and clarity (selectivity). It is desirable to decrease the charge pump operating speed from the standpoint of noise reduction. However, the charge pump operating frequency is dictated by the comparison frequency. As the comparison frequency increases, the noise floor of the charge pump is raised. Hence, there exists a trade-off between the charge pump operating frequency and the noise performance.
In view of the above, there is a need for a low noise charge pump that overcomes the problems of the related art.